This invention relates to methods of manufacturing an electronic device comprising thin-film transistors formed on a substrate. The device may be, for example, a liquid crystal display or other flat panel display, or any other type of large area electronic device, for example, a thin-film data store or an image sensor. The invention also relates to such electronic devices manufactured by such methods.
There is currently much interest in developing thin-film field-effect transistors (hereinafter termed "TFTs") on glass and other insulating substrates for large area electronics applications, for example flat panel displays. Such TFTs fabricated with amorphous or polycrystalline semiconductor films may form, for example, switching elements of a cell matrix, e.g. as described in published European patent application EP-A-0 464 897 (our reference PHB 33646), the whole contents of which are hereby incorporated herein as reference material. A recent development involves the fabrication and integration of circuits from TFTs (often using polycrystalline silicon), for example integrated drive circuits for the matrix of a flat-panel display.
In the manufacture of such electronic devices, it is usual to form thin-film transistors on a substrate by steps which include: (a) depositing a disordered material on the substrate to provide a semiconductor film in which channel regions of the transistors are to be accommodated, charge-trapping states being present in the semiconductor film, (b) providing a masking pattern on the semiconductor film to mask areas where the thin-film transistors are to be formed, (c) etching away the unmasked areas of the film from the substrate to leave semiconductor film bodies for the transistors, and (d) providing the semiconductor film bodies with electrodes forming a source, a drain and an insulated gate of each transistor, the transistor current flow through the channel region between the source and drain being by charge carriers of a first conductivity type under the control of the insulated gate in operation of the transistor.
For polycrystalline silicon TFTs, the semiconductor film may be deposited as polycrystalline silicon, or it may be deposited as amorphous silicon which is subsequently converted in situ on the substrate into polycrystalline silicon by heating either in a furnace or with a laser beam. However, even when the resulting film is of large grain polycrystalline silicon, it has a high density of charge trapping states due to the disorder in the film. These charge trapping states cause the material to behave quite differently from monocrystalline silicon. Thus, for example, TFTs (even with large-grain polycrystalline silicon) have a. high leakage current and a high threshold voltage as compared with field-effect transistors formed in monocrystalline silicon. Furthermore low doping levels have little or no effect in changing the generally intrinsic conductivity type of the film which results from the high density of trapping levels near the middle of the bandgap of the semiconductor material. However it is known that passivating treatments can be (and preferably are) carried out on the disordered thin-film semiconductor material to improve its properties. Thus, in the case of polycrystalline silicon, a hydrogenation treatment is usually effected to passivate the trapping states at the grain boundaries.
In order to secure a reduction in the leakage current of a TFT, it is known from published European patent application EP-A-0 408 129 (our reference PHB33571) to implant dopant of a second conductivity type (opposite to that of the charge-carriers of the conduction channel) at the back of the channel region. The whole contents of EP-A-0 408 129 are hereby incorporated herein as reference material. Such a dopant implantation may be effected either before or after the etching step (c) to define the film bodies for the transistors. This treatment is remarkably effective. However even after providing such an implant and passivating the grain boundaries, the Applicant now finds that there remains a leakage current whose magnitude it would be desirable to reduce even further. The Applicant finds that although the leakage current decreases with decreasing width of the channel region (i.e. reducing the volume of material), there remains a current level for a given film thickness beyond which it does not seem possible to reduce the leakage current by these known means.
There appears to be a variety of effects which both individually and in combination result in a significant edge leakage current along the side-wall of the channel region. These effects arise both from the nature of the thin-film materials and processes used in TFT manufacture and from the TFT structure. Both mobile ion effects and charge carrier trapping effects appear to be involved. The topographical structure of the top (or bottom) surface of the thin-film body adjacent to the insulated gate is determined (inter alia) by the material deposition and growth, whereas the structure of the edges (i.e. the side walls) of the TFT body is determined by the etching away of the material in step (c). This etched edge of the disordered material has different properties and can absorb different impurities, as compared with the top and bottom surfaces. As already mentioned, the TFT channel region has a high density of trapping states due to the disordered nature of its semiconductor material. Charge may be trapped in surface states at an interface between the disordered semiconductor material and the gate insulating layer where it extends on the edge of the TFT body. When the drain is reverse-biased in the off state of the TFT, extra generation of electron-hole pairs may occur in the field area at the edge of the channel region between the gate and the drain. Leakage current due to field-enhanced generation of carriers increases with drain bias. Furthermore, the gate insulating layer may have a contributing effect; for example, if the deposited insulated layer is thinner at the edge of the channel region, a higher field results in this area between the gate and drain. The paper "Water-Related Instability In TFTs Formed Using Deposited Gate Oxides" by N. D. Young and A. Gill in Semicond. Sci. Technol. Vol 7 (1992) pages 1003 to 1108, published by IOP Publishing Ltd in the UK, also describes an instability effect involving the build-up of ions on the side-walls (edges) of the channel regions due to water diffusion into the undensified gate oxide insulating layer. The whole contents of this paper are hereby incorporated herein as reference material.